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18. November 2025 /

We introduce a CMOS current reference with intrinsic curvature compensation and exceptional PVT stability, requiring only a single-point batch trim. Silicon measurements in 130 nm SOI validate ~100 ppm/°C TC at µA current levels.

A. Sakr, M. A. Hassan and J. Anders, "A PVT-Tolerant, Curvature-Compensated CMOS Bandgap-Based Current Reference With Single-Point Batch Trim," in IEEE Open Journal of the Solid-State Circuits Society, doi: 10.1109/OJSSCS.2025.3633660.

Article (Open Access)

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