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Sakr, Ayman

Ayman Sakr

M. Sc.

Akademischer Mitarbeiter
Institut für Intelligente Sensorik und Theoretische Elektrotechnik

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+49 711 685 61617
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Pfaffenwaldring 47
70569 Stuttgart
Deutschland
Raum: 3.138

Publikationen

Zeitschriften, Konferenzen und Bücher:

2022
1. T. Elrifai, A. Sakr, H. Lotfi, M. A. Hassan, K. Lips, und J. Anders, „A 7 GHz VCO-based EPR spectrometer incorporating a UWB data link“, in 2022 20th IEEE Interregional NEWCAS Conference (NEWCAS), in 2022 20th IEEE Interregional NEWCAS Conference (NEWCAS). Juni 2022, S. 280–284. doi: 10.1109/NEWCAS52662.2022.9842254.
  - BibTeX
  - DOI
  BibTeX
  @inproceedings{9842254, abstract = {This paper presents an electron paramagnetic resonance (EPR) detection system that can wirelessly transmit continuous wave (CW) EPR data over distances up to 30 cm with minimal degradations in SNR. The proposed system comprises a VCO-based EPR-on-a-chip (EPRoC) sensor with a spin sensitivity of $2 \times {10^{12}}\;{\text{spins}}/\sqrt {{\text{Hz}}} $, a 14-bit oversampling ΣΔ-modulator, a 7 GHz bandwidth-tunable ultra-wideband (UWB) transmitter chip, and a custom-designed 2 GHz-bandwidth elliptical dipole antenna. On the receiver side, we directly digitize the antenna signal and recover the EPR signal in the digital domain via a discrete Fourier transform (DFT)-based demodulation scheme. The presented platform is the first wirelessly connected EPR detection system that allows for in-situ EPR experiments using EPRoC detectors under variable operation conditions while enabling direct wireless access to the experimental data. The estimated bit error rate (BER) of the link at a distance of 10 cm from the transmitter is 1×10<sup>-7</sup>.}, author = {Elrifai, Tarek and Sakr, Ayman and Lotfi, Hadi and Hassan, Mohamed Atef and Lips, Klaus and Anders, Jens}, booktitle = {2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)}, doi = {10.1109/NEWCAS52662.2022.9842254}, month = {06}, pages = {280-284}, title = {A 7 GHz VCO-based EPR spectrometer incorporating a UWB data link}, year = 2022 }
  DOI
  10.1109/NEWCAS52662.2022.9842254
2. A. Sakr, M. A. Hassan, K. Khan, M. Kern, und J. Anders, „A distributed amplitude control loop for VCO-array-based EPR-on-a-chip detectors“, in 2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), in 2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME). Juni 2022, S. 13–16. doi: 10.1109/PRIME55000.2022.9816840.
  - BibTeX
  - DOI
  BibTeX
  @inproceedings{9816840, abstract = {This paper presents an amplitude control loop (ACL) for VCO-array-based electron paramagnetic resonance (EPR) detectors. The proposed ACL enhances the microwave magnetic field (B<inf>1</inf>) stability over the whole VCO frequency sweep range, against different sample environments and at varying experimental conditions. By introducing a distributed amplitude detection scheme, the proposed ACL implementation can regulate B<inf>1</inf> field intensities in injection-locked VCO arrays with reduced loading effects and minimal phase noise degradation. Extracted-level circuit simulations on an example VCO array implementation demonstrate the functionality and excellent achievable performance of the proposed approach.}, author = {Sakr, Ayman and Hassan, Mohamed Atef and Khan, Khubaib and Kern, Michal and Anders, Jens}, booktitle = {2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)}, doi = {10.1109/PRIME55000.2022.9816840}, month = {06}, pages = {13-16}, title = {A distributed amplitude control loop for VCO-array-based EPR-on-a-chip detectors}, year = 2022 }
  DOI
  10.1109/PRIME55000.2022.9816840
2021
1. M. A. Hassan, T. Elrifai, A. Sakr, M. Kern, K. Lips, und J. Anders, „A 14-channel 7 GHz VCO-based EPR-on-a-chip sensor with rapid scan capabilities“, in 2021 IEEE Sensors, in 2021 IEEE Sensors. Okt. 2021, S. 1–4. doi: 10.1109/SENSORS47087.2021.9639513.
  - BibTeX
  - DOI
  BibTeX
  @inproceedings{9639513, abstract = {This paper presents a VCO-based EPR-on-a-chip (EPRoC) sensor for portable, battery-operated electron paramagnetic resonance (EPR) spectrometers. The proposed chip contains an array of 14 injection-locked VCOs as the sensing element for an improved sensitive volume and phase noise performance. By cointegrating a high-bandwidth PLL, the presented design allows for continuous-wave and rapid-scan EPR experiments with a minimum number of external components. The active loop filter introduces an assisted replica charge pump that mitigates the slewing requirements on the loop-filter amplifier. The measured spin sensitivity of 2×10<sup>9</sup> spins/$\sqrt {{\text{Hz}}} $ together with the large active volume of 210 nl lead to an 8-fold improvement in concentration sensitivity compared to the state-of-the-art in EPRoC detectors.}, author = {Hassan, Mohamed Atef and Elrifai, Tarek and Sakr, Ayman and Kern, Michal and Lips, Klaus and Anders, Jens}, booktitle = {2021 IEEE Sensors}, doi = {10.1109/SENSORS47087.2021.9639513}, issn = {2168-9229}, month = {10}, pages = {1-4}, title = {A 14-channel 7 GHz VCO-based EPR-on-a-chip sensor with rapid scan capabilities}, year = 2021 }
  DOI
  10.1109/SENSORS47087.2021.9639513
2. A. Sakr, M. A. Hassan, und J. Anders, „A 93.1-dB SFDR, 90.3-dB DR, and 1-MS/s CT Incremental Sigma-Delta Modulator Incorporating a Resistive Dual-RTZ FIR DAC“, in ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), in ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC). Sep. 2021, S. 211–214. doi: 10.1109/ESSCIRC53450.2021.9567762.
  - BibTeX
  - DOI
  BibTeX
  @inproceedings{9567762, abstract = {This paper presents a high-bandwidth, high-resolution continuous-time incremental ΣΔ-modulator employing a 6-tap finite impulse response (FIR) feedback digital-to-analog converter (DAC) for improved clock jitter immunity. Resetting the FIR filter internal states in the incremental mode introduces initial transient overshoots, which can cause instability at high input amplitudes. To solve this problem, we propose the use of a purely resistive feedthrough path from the overall input to the second integrator input. This additional path alleviates the large transient swings associated with the incremental operation and extends the modulator's dynamic range (DR). Furthermore, we introduce a novel implementation of a fully differential dual return-to-zero (RTZ) resistive FIR DAC that eliminates inter-symbol interference (ISI) signal-dependent errors and, thereby, improves modulator linearity. The presented design is fabricated in a 180-nm SOI CMOS technology and achieves a DR of 90.3 dB and a peak spurious-free DR of 93.1 dB at a Nyquist conversion rate of 1 MS/s. The power dissipated from a 1.8-V power supply is 8.06 mW, resulting in a Schreier FoM of 168.3 dB.}, author = {Sakr, Ayman and Hassan, Mohamed Atef and Anders, Jens}, booktitle = {ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)}, doi = {10.1109/ESSCIRC53450.2021.9567762}, month = {09}, pages = {211-214}, title = {A 93.1-dB SFDR, 90.3-dB DR, and 1-MS/s CT Incremental Sigma-Delta Modulator Incorporating a Resistive Dual-RTZ FIR DAC}, year = 2021 }
  DOI
  10.1109/ESSCIRC53450.2021.9567762
2019
1. A. Mohamed, A. Sakr, und J. Anders, „FIR Feedback in Continuous- Time Incremental Sigma-Delta ADCs“, in 2019 17th IEEE International New Circuits and Systems Conference (NEWCAS), in 2019 17th IEEE International New Circuits and Systems Conference (NEWCAS). Juni 2019, S. 1–4. doi: 10.1109/NEWCAS44328.2019.8961214.
  BibTeX
  @inproceedings{8961214, abstract = {In this paper, we present a new method to include finite-impulse-response (FIR) feedback digital-to-analog converters (DACs) in continuous-time (CT) Incremental Sigma-Delta (I-ΣΔ) analog-to-digital converters (ADC), which minimizes transient overshoots and thereby maximizes the modulator's stability. More specifically, it can be shown that increasing the number of FIR taps in I-ΣΔ feedback DACs could lead to instability or a reduced maximum stable amplitude (MSA), even when using a proper compensation path. However, by presetting the FIR feedback to a voltage close to the input signal, a larger number of FIR taps can be used, increasing the jitter robustness of the CT I-ΣΔ. This presetting is achieved using a low resolution Nyquist rate ADC to preset the FIR taps. Moreover, presetting the FIR feedback slightly increases the modulator's MSA and signal-to-noise ratio compared to a non-return-to-zero (NRZ) feedback. To validate the proposed presetting approach, a third-order I-ΣΔ-ADC employing a 12-tap FIR DAC with presetting using a 4-bit flash ADC is compared against a conventional NRZ DAC and a conventional FIR DAC without presetting in MATLAB/Simulink.}, author = {{Mohamed}, A. and {Sakr}, A. and {Anders}, J.}, booktitle = {2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)}, doi = {10.1109/NEWCAS44328.2019.8961214}, month = {06}, pages = {1-4}, title = {FIR Feedback in Continuous- Time Incremental Sigma-Delta ADCs}, url = {https://ieeexplore.ieee.org/document/8961214/}, year = 2019 }
  Link
  https://ieeexplore.ieee.org/document/8961214/
  DOI
  10.1109/NEWCAS44328.2019.8961214
2016
1. A. S. Sakr, A. H. Madian, und S. H. Ismail, „Full implementation of a capacitance-to-digital converter system based on SAR logic and charge redistribution technique“, in 2016 28th International Conference on Microelectronics (ICM), in 2016 28th International Conference on Microelectronics (ICM). Dez. 2016, S. 245–248. doi: 10.1109/ICM.2016.7847861.
  BibTeX
  @inproceedings{7847861, abstract = {This paper demonstrates a low power 6-bit single-ended voltage-based Capacitance-to-Digital Converter (CDC) circuit based on a charge redistribution technique and Successive Approximation Register (SAR) logic operating at 370 kHz sampling rate. A proposed realization of a SAR logic control unit integrated with a low power comparator is introduced where the system blocks are entirely built on the transistor level. The system, which is fully automated with a universal clock signal, is tested for real time Cadence simulations using a 130nm model from which static and dynamic parameters are extracted. The average static and dynamic current consumption becomes in the order of 200μA using a 1.2V power supply. The tested specifications are compared with a similar CDC implementation and proved an overall enhancement and superiority on both power consumption and conversion rate performance metrics.}, author = {{Sakr}, A. S. and {Madian}, A. H. and {Ismail}, S. H.}, booktitle = {2016 28th International Conference on Microelectronics (ICM)}, doi = {10.1109/ICM.2016.7847861}, month = {12}, pages = {245-248}, title = {Full implementation of a capacitance-to-digital converter system based on SAR logic and charge redistribution technique}, url = {https://ieeexplore.ieee.org/document/7847861/}, year = 2016 }
  Link
  https://ieeexplore.ieee.org/document/7847861/
  DOI
  10.1109/ICM.2016.7847861

Ayman Sakr

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