Master Theses

Topics

Medical engineering

Supervisor: Dr.-Ing. André Buchau

Several topics for master theses in the field of medical engineering in cooperation with BOWA-electronic GmbH & Co. KG are listed at the german version of this page.

 (c) BOWA-electronic GmbH & Co. KG

Design and Implementation of a Power-Efficient High-Resolution Incremental Sigma Delta ADC

Incremental Sigma Delta ADCs (ISD ADCs) are becoming popular for sensing applications requiring high-resolution data converters. Moreover, their benefits extend to multi-channel sensor applications, where different uncorrelated data streams from each sensor are processed by a single ADC. Here, a multiplexed ISD ADC can significantly enhance the energy efficiency of the overall system. One example of such an application is neural recording, where a large number of spin electronics sensors are used to record the magnetic field activity for neuronal investigation. Since these experiments are performed in vivo (within the living animal), a low power consumption is of prime importance. Hence, novel design architectures are needed that bring down the power consumption of the overall system, cf. Figure 1.

In this project, you will design a power-efficient, high-resolution Incremental Sigma Delta ADC. This includes system-level design of the ADC in MATLAB and Simulink as well as the transistor-level design of the modulator in Cadence Virtuoso.

Requirements:

  • Basic knowledge in analog CMOS circuit design is mandatory.
  • Basic experience in Cadence Virtuoso is mandatory.
  • Basic experience in MATLAB and Simulink is a plus.

What we expect: Motivation, dedication and the curiosity to explore new approaches

What we provide: Access to state-of-the-art design tools and the possibility to participate in a research project with leading academic partners in France and Germany

Contact: M.Sc. Ayman Mohamed

 (c)
Incremental Sigma Delta ADC is a prominent candidate for high-resolution multi-channel sensor applications

Design of a Low-Noise, Low-Offset Amplifier for Neuronal Current Imaging

The ongoing research in neural recording systems has been driven by current advancements in neuroscience aiming at single-event detection at the neuronal scale. Spin electronics sensors are superior candidates for both sensitive and miniaturized sensors as they are needed for neuronal investigation due to their low noise properties. This creates a challenge on the front-end design of the signal conditioning circuitry requiring a low-noise and low-offset performance as well as a large gain to efficiently amplify the weak neuronal signals.

In this project, you will design a low-noise, low-offset variable-gain instrumentation amplifier in the Cadence Virtuoso design environment. To achieve a low-noise and low-offset performance, dynamic offset cancellation techniques will also have to be incorporated into the design.

Requirements:

  • Basic knowledge in analog CMOS circuit design is mandatory
  • Basic experience in Cadence analog design software tools is mandatory

 What we expect: Motivation, dedication and the curiosity to explore new approaches

What we provide: Access to state-of-the-art design tools and the possibility to participate in a research project with leading academic partners in France (CEA) and Germany (MPI Frankfurt)

Contact: M.Sc. Ayman Mohamed

 (c)
The neuronal current generates a magnetic field which can be detected by a magnetic sensor and processed by the front-end electronics

Integrated Wideband Phase-locked Loop for Electron Spin Resonance Detection

Recent publications have shown the great potential of integrated LC-VCOs for the detection of electron spin resonance (ESR) experiments in the rapid-scan and even pulsed mode. Here, to eliminate the frequency shift of the VCO due to PVT (process, voltage and temperature) variations, the VCO should be embedded into a phase-locked loop (PLL) to lock its frequency to a stable reference oscillator. The aim of this project is to analyze and design a wideband PLL that is capable of a wideband FM modulation and at the same time can demodulate the ESR signal. The PLL design will be combined with our existing spin model to perform transistor-level transient ESR simulation.

The candidate will have the chance to work with industry-standard IC design tools such as Cadence Virtuoso and Keysight’s GoldenGate. If successful, the thesis results will be incorporated into a future tape-out, targeting high-impact scientific conferences and journals.

We expect candidates to have previous knowledge in IC design, especially RFIC and display a strong motivation, responsibility and open-mindedness.

Contact person: M.Sc. Anh Chu

Contact

 

Institute of Smart Sensors

Pfaffenwaldring 47, Stuttgart

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